The scaling of VLSI circuits is a constant effort. Smaller integrated circuits allow for more devices to be formed in one semiconductor chip. Additionally, the power consumption and the performance of the devices are also improved. With the circuits becoming smaller and faster, the improvement in device driving current is becoming more important, which device driving current can be increased by improving carrier mobility. Among efforts made to enhance carrier mobility, forming a stressed channel region is a known practice. The performance of a Metal-Oxide-Semiconductor (MOS) device can be enhanced through increasing the stress in the respective channel. This technique allows for the performance of the MOS device to be improved without adding complexity to circuit fabrication or design.
Research has revealed that a bi-axial, in-plane tensile stress can improve N-type MOS (NMOS) performance, and a compressive stress parallel to the channel length direction can improve P-type MOS (PMOS) device performance. A commonly used method for applying stress to the channel region is forming a stressed Contact Etch Stop Layer (CESL) on a MOS device. The stressed CESL applies a stress into the channel region. Therefore, the carrier mobility in the channel region is improved.
Since NMOS devices prefer tensile stresses in their channel regions, and PMOS devices prefer compressive stresses, tensile CESLs may be formed on the NMOS devices, and compressive CESLs may be formed on the PMOS devices. The stresses applied on each of the PMOS devices and NMOS devices are thus affected by the magnitude of the inherent stresses of the respective overlying CESLs.